1. Field of the Invention
The present invention relates to a circuit, a use, and a method for controlling a receiver circuit.
2. Description of the Background Art
A receiver with a digital phase-locked loop is known from IEICE TRANS. COMMUN., Vol. 84-B, No. 1, pp. 26-35, January 2001, “Demodulation of CPFSK and GMSK Signals Using Digital Signal Processing DPLL with Sequence Estimator.” The digital phase-locked loop (DPLL) has a subtractor, which subtracts a feedback phase, generated in the loop, from an input phase. The phase difference obtained by the subtraction is called a phase error. The digital phase-locked loop is part of a demodulator, which demodulates a signal for a decision circuit for obtaining data from an in-phase part and a quadrature phase part of a baseband signal.
Receivers of this type can be used for, for example, the transmission of measured data, for motor vehicle access systems, or for satellite communication.